1. Field of the Invention
The present invention relates to a semiconductor equipment with an internal circuit operating in synchronism with a system clock signal.
2. Description of the Related Art
In an internal circuit of a semiconductor equipment, an internal element repeats switching at high speed in synchronism with a signal called as a system clock. As a result of this, harmonic currents flow in the internal circuit and the harmonic currents flow out to outside to cause problems such as electromagnetic interference.
Following the increase in complexity of integration in a semiconductor equipment in recent years, a circuit scale has become larger and a synchronization design takes a dominant position in LSI design methods. This synchronization design method is such that an operation timing in the internal circuit is fixed at one of a rise and fall of a system clock to thereby enjoy an advantage that introduction of static timing verification is enabled, leading to better efficiency in timing design and improved completeness of timing design.
On the other hand, as a constraint accompanying this advantage, a necessity arises that a system clock is required to simultaneously change in all regions in the internal circuit. Therefore, timing compensation in propagation of a system clock in the internal circuit is ensured by application of a technique such as CTS (clock tree synthesis).
Along with the increase in circuit scale, a circuit scale of CTS also becomes larger, which though it is natural, enhances a consumed current in CTS and further, results in a state where power supply harmonics generated by the CTS circuit cannot be neglected.
Description will be given of a conventional semiconductor equipment with an internal circuit operating in synchronism with a system clock signal below.
FIG. 19 shows a conventional semiconductor equipment.
In a semiconductor chip 101 as a semiconductor equipment, a numerical symbol 2 is an oscillating circuit section to which an oscillator or an oscillating unit is connected. A numerical symbol 4 is an internal circuit of the semiconductor chip 101, which is constituted of a CTS circuit 5 to which a system clock from the oscillating circuit section 2 is inputted and an operation circuit section 6 operating in synchronism with the system clock signal that is outputted from the CTS circuit 5 and that has been timing-adjusted.
FIG. 20 is a signal waveform diagram of the semiconductor equipment shown in FIG. 19 and FIG. 21 is a current spectrum chart thereof.
A system clock generated in the oscillating circuit section 2 is compensated with respect to a timing of a signal change in the CTS circuit 5 and is simultaneously inputted to all of circuit elements constituting the operation circuit section 6.
All of the circuit elements constituting the operation circuit section 6 simultaneously start signal changes at a leading edge of the system clock.
On the other hand, generated in a CMOS circuit is a charging/discharging current required for changes in potential of a through current and a signal line respectively in transition of the signal.
Therefore, in the CTS circuit 5, as shown in FIG. 20, a current is consumed at each of a leading edge and trailing edge of the system clock, while in the operation circuit section 6, a current is consumed only at an leading edge of the system clock. FIG. 21 shows a present state of generation of upper harmonics in a case where a duty ratio is 50%. In FIG. 21, the first current component in the current spectrum is the second harmonic of the system clock and the next current component therein is the fourth harmonic thereof.
With further increase in circuit scale, the CTS circuit 5 also becomes larger and a proportion of a total consumed current in the semiconductor chip 101 accounted for by a consumed current in the CTS circuit 5 has been more and more increased partly because of a transition probability of a signal is 100%.
Herein, since a current in the CTS circuit 5 is consumed at each timing of a leading edge and a trailing edge, a current change occurs at a frequency twice that of the system clock. As a consumed current in the semiconductor chip 101, harmonics are generated based on a frequency twice that of the system clock. As a result, harmonics of an even number order of the system clock increase in amount.
The present invention has been made in order to solve the problem and it is an object of the present invention to provide a semiconductor equipment with less electromagnetic interference.